This invention relates generally to silicon (Si) and III-V compound semiconductor microfabrication processes, and more particularly relates to processes enabling the monolithic integration of electronic and optoelectronic silicon and III-V semiconductor devices.
It is well recognized that the monolithic integration of silicon integrated electronic circuits and III-V semiconductor electronic and optical devices is an important technological challenge for enabling a wide range of applications. For example, monolithic integration of III-V laser diodes and p-i-n detectors with high density, high performance silicon complementary metal oxide semiconductor (CMOS) circuitry is desired to produce robust optoelectronic integrated circuits. Much research has been directed in particular to Si integration with the III-V compound gallium arsenide (GaAs) due to wide applicability of GaAs for high performance optical and electronic devices.
Historical efforts to monolithically integrate GaAs with Si have largely focused on the heteroepitaxial growth of GaAs on a silicon substrate. Only limited success has resulted for such heteroepitaxial growth, however, due to the lattice constant mismatch between Si and GaAs. This Si-GaAs lattice constant mismatch inhibits the ability to produce an abrupt and defect free interface of one material grown on the other. Lattice constant mismatch exists between Si and other III-V materials as well and in general is understood to limit the success of heteroepitaxial processing.
Aside from lattice constant mismatch, a more difficult materials processing challenge is posed by the very large difference in thermal expansion coefficient between Si and most III-V materials such as GaAs. GaAs is characterized by a thermal expansion coefficient that is much larger than that of Si; as a result, a GaAs layer expands more than a Si layer when exposed to an increase in temperature. During cooling of composite GaAs/Si layers, the increased contraction rate of the GaAs layer over that of the Si layer produces stress that can cause materials defects at the interface of the two layers and that can cause lattice distortion in the bulk of the two materials. In general, the densities of such bulk and interface defects are unacceptable for typical device applications, including optoelectronic device applications.
While there have been proposed a range of techniques for reducing the number and impact of Si/III-V interface defects generated due to lattice constant mismatch, it is currently very difficult to suppress or to accommodate the very large stresses and associated defects that are induced in III-V epitaxial layers on Si by even relatively small temperature changes. But many conventional microfabrication techniques for producing Si CMOS devices generally require high-temperature processing steps.
Various techniques for bonding III-V materials and Si have been proposed for overcoming lattice constant mismatch and thermal expansion coefficient differences. These techniques generally require complicated configurations of stress relief interface layers and/or employ only low-temperature bonding processes that result in suboptimal strength of composite structures. Efforts at monolithic integration of Si and III-V materials have been hampered by the complexity, restrictions, and limitations of these proposed bonding processes.
The invention provides processes that enable robust bonding of Si and III-V materials in a manner that accommodates formation of electronic and optoelectronic devices on the materials and that accommodates monolithic microfabrication processing on the bonded materials. In accordance with the invention, a silicon substrate is contacted together with a III-V material substrate and the contacted substrates are annealed at a first temperature that is above ambient temperature, e.g., at a temperature of between about 150xc2x0 C. and about 350xc2x0 C. The silicon substrate is then thinned.
The silicon substrate can be provided as, e.g., a silicon-on-insulator (SOI) substrate configuration, a separation-by-implantation-of-oxygen (SIMOX) substrate configuration, or other selected configuration, preferably accommodating thinning of the silicon substrate. The III-V material substrate can be provided as, e.g., a GaAs substrate, an InP substrate, or other selected III-V substrate.
The bonding process provided by the invention enables the fabrication of thick, strain-sensitive and defect-sensitive optoelectronic devices on the optimum substrate for such, namely, a thick III-V material substrate, while enabling the fabrication of Si electronic devices in a thin Si layer, resulting from the thinned Si substrate, that is sufficient for such fabrication but which has been thinned to eliminate thermally-induced stress in both the Si and III-V materials. The III-V material substrate thickness thereby provides the physical strength of the composite substrate structure, while the thinned silicon substrate minimizes stress in the composite structure.
In accordance with the invention, silicon electronic devices can be fabricated on the silicon substrate before contacting the silicon substrate with the III-V material substrate, and silicon electronic devices further can be fabricated on the silicon layer resulting from thinning of the silicon substrate. Similarly, III-V material electronic devices can be fabricated on the III-V material substrate before contacting the III-V material substrate with the silicon substrate, and III-V material electronic devices can further be fabricated on the III-V substrate after thinning of the silicon substrate. An electrical interconnection can be fabricated between the silicon and III-V material electronic devices. III-V material optical devices can be fabricated on the III-V material substrate before contacting the III-V material substrate with the silicon substrate, and III-V material optical devices further can be fabricated on the III- V substrate after thinning of the silicon substrate. Such optical device fabrication can include, e.g., growth of a heteroepitaxial layer on the III-V material substrate.
In accordance with the invention, a dielectric layer can be formed on at least one of the silicon and III-V material substrate surfaces to be contacted together. Preferably, a dielectric layer is formed on both the silicon and III-V material substrate surfaces to be contacted together. The dielectric layer can be provided as, e.g., an oxide layer, a nitride layer, or other suitable layer.
Further in accordance with the invention, the silicon and III-V material substrate surfaces to be contacted together can be rendered hydrophilic. During contacting together of the surfaces, pressure can be applied to the silicon and III-V material substrates.
Thinning of the silicon substrate can be carried out e.g., to thin the silicon substrate to a thickness less than about 1 micron. Preferably the silicon substrate is thinned to a thickness less than about 5000 angstroms, and more preferably, the silicon substrate is thinned to a thickness less than about 2000 angstroms.
After the silicon substrate is thinned, in accordance with the invention the III-V material substrate and the thinned silicon substrate can be annealed at a second temperature that is greater than the first temperature. The second anneal temperature can be, e.g., greater than about 200xc2x0 C., more preferably, greater than about 350xc2x0 C. The second anneal temperature can also be that temperature at which further thermal processing of the substrates is to be carried out.
The bonding process of the invention enables monolithic integration of Si electronics, e.g., CMOS electronics, with high-performance III-V material optoelectronic devices such as laser diodes and photodetectors as well as III-V material electronic devices such as MESFET and HEMT devices, in a configuration that is mechanically robust to thermal processing. As a result, a wide range of applications, including communications and optical systems, are well-addressed by the invention.
Other features and advantages of the invention will be apparent from the following detailed description and accompanying drawings, and from the claims.